Wear-leveling method for cross-point memory for multiple data temperature zones

ABSTRACT

A method performed by a processor to improve wear-leveling in a cross-point (X3D) memory, comprises detecting, by a processor coupled to the X3D memory, a trigger event, wherein the X3D memory comprises a first section of memory units and a second section of memory units, and in response to detecting the trigger event, relocating, by the processor, data stored in a first memory unit of the first section of memory units to a memory unit adjacent to a last memory unit of the first section of memory units, and relocating, by the processor, data stored in a first memory unit of the second section of memory units to a memory unit adjacent to a last memory unit of the second section of memory units.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to U.S. Provisional PatentApplication 62/379,228, filed Aug. 24, 2016 by Xiangyu Tang, Ken Hu,Xiaobing Lee, and Yunxiang Wu, and entitled “Wear-Leveling Method forCross-Point Memory for Multiple Data Temperature Zones,” and U.S.Provisional Patent Application 62/382,581, filed Sep. 1, 2016 by XiangyuTang, Ken Hu, Xiaobing Lee, and Yunxiang Wu, and entitled “Wear-LevelingMethod for Cross-Point Memory for Multiple Data Temperature Zones,” bothof which are incorporated herein by reference as if reproduced in itsentirety.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not applicable.

REFERENCE TO A MICROFICHE APPENDIX

Not applicable.

BACKGROUND

The wear on memory cells, or physical locations, within a memory systemvaries depending upon how often each of the cells is programmed. If acell or, more generally, a memory unit, is programmed once and theneffectively never reprogrammed, the wear associated with that cell willgenerally be relatively low. However, if a cell is repetitively writtento and erased, the wear associated with that cell will generally berelatively high. As logical block addresses (LBAs) are used by hosts,the same physical locations or cells within the flash memory system arerepeatedly written to and erased if a host repeatedly uses the same LBAsto write and overwrite data.

When some cells are effectively worn out while other cells arerelatively unworn, the existence of the worn out cells generallycompromises the overall performance of the flash memory system. Inaddition to degradation of performance associated with worn out cellsthemselves, the overall performance of the memory system may beadversely affected when an insufficient number of cells which are notworn out are available to store desired data. Often, a memory system maybe deemed unusable when a critical number of worn out cells are presentin the memory system, even when many other cells in the flash memorysystem are relatively unworn.

To increase the likelihood that cells within a flash memory system areworn fairly evenly, wear-leveling operations are often performed.Wear-leveling operations are generally arranged to allow the cells whichare associated with particular LBAs to be changed such that the sameLBAs are not always associated with the same cells. By changing the cellassociations of LBAs, it is less likely that a particular cell may wearout well before other cells wear out.

SUMMARY

Cross-point (X3D) memory includes memory units that can be updatedwithout having to read, erase, and program other memory. Therefore,including an X3D memory in a mobile device provides for faster ways toaccess and update data using the mobile device. However, current X3Dtechnology does not implement wear-leveling mechanism to increase thelifespan of the X3D memory. Embodiments of the present disclosureinvolve configuring a plurality of first contiguous memory units assmall memory units (SMUs) storing hot data and configuring a pluralityof second contiguous memory units as large memory units (LMUs) storingwarm or cold data. During each iteration of wear-leveling, hot datastored at a first SMU of the SMUs switches locations with warm/cold datastored at a first LMU of the LMUs. Switching the storage locations ofhot data with warm/cold data help ensure that the memory cells of thoselocations wear out at substantially the same rate. In addition, the datastructures stored at the SMUs and LMUs will maintain their relativesequential order due to the contiguous nature of the SMUs and LMUs.

In one example embodiment, the disclosure includes a method performed bya processor to improve wear-leveling in an X3D memory, comprisingdetecting, by a processor coupled to the X3D memory, a trigger event,wherein the X3D memory comprises a first section of memory units and asecond section of memory units, the first section of memory unitscomprises a plurality of contiguous memory units configured to storedata of a first type, and the second section of memory units comprises aplurality of memory units configured store data of a second type, and inresponse to detecting the trigger event, relocating, by the processor,data stored in a first memory unit of the first section of memory unitsto a memory unit adjacent to a last memory unit of the first section ofmemory units, and relocating, by the processor, data stored in a firstmemory unit of the second section of memory units to a memory unitadjacent to a last memory unit of the second section of memory units. Insome embodiments, the disclosure also includes wherein the trigger eventoccurs when at least one of a frequency of accesses to one or more ofthe plurality of contiguous memory units in the first section of memoryunits reaches a pre-determined threshold, and/or wherein the triggerevent occurs according to a pre-determined schedule indicating when anext iteration of wear-leveling needs to be performed on the X3D memory,and/or wherein the memory unit adjacent to the last memory unit of thefirst section of memory units is at least one of the first memory unitof the second section of memory units or an empty memory unit, and/orwherein relocating the data stored in the first memory unit of the firstsection of memory units to the memory unit adjacent to the last memoryunit of the first section of the memory units comprises relocating thedata stored in the first memory unit of the first section of memoryunits to a location of the first memory unit of the second section ofmemory units, and/or wherein relocating the data stored in the firstmemory unit of the second section of memory units to the memory unitadjacent to the last memory unit of the second section of memory unitscomprises relocating the data stored in the first memory unit of thesecond section of memory units to a location of the first memory unitsof the first section of memory units, and/or wherein an empty memoryunit is located between the last memory unit of the second section ofmemory units and the first memory unit of the first section of memoryunits, wherein relocating the data stored in the first memory unit ofthe first section of memory units to the memory unit adjacent to thelast memory unit of the first section of memory units comprisesrelocating the data stored in the first memory unit of the first sectionof memory units to the location of the first memory unit of the secondsection of memory units, and wherein relocating the data stored in thefirst memory unit of the second section of memory units to the memoryunit adjacent to the last memory unit of the second section of memoryunits comprises relocating, by the processor, the data stored in firstmemory unit of the second section of memory units to the empty memoryunit, and erasing, by the processor, the data stored in the first memoryunit of the first section of memory units such that the first memoryunit of the first section of memory units becomes the empty memory unit,and/or wherein the first section of memory units comprises a pluralityof SMUs configured to store a first type of data, wherein the secondsection of memory units comprises a plurality of LMUs configured tostore a second type of data, wherein the X3D memory further comprises athird section of memory units, and wherein the third section of memoryunits comprises a plurality of medium memory units (MMUs) configured tostore a third type of data.

In another example embodiment, the disclosure includes an X3D memorysystem, comprising a plurality of SMUs stored in contiguous locations inthe X3D memory and configured to store data of a first type, a pluralityof LMUs stored in contiguous locations in the X3D memory and configuredto store data of a second type, and at least one processor that detectsa trigger event, wherein the at least one processor, in response to thetrigger event, relocates data stored in a first SMU of the plurality ofSMUs to a memory unit adjacent to a last SMU of the plurality of SMUs,wherein the plurality of SMUs are stored in contiguous locations in theX3D memory system, and relocates data stored in a first LMU of theplurality of LMUs to a memory unit adjacent to a last LMU of theplurality of LMUs, wherein the plurality of LMUs are stored incontiguous locations in the X3D memory system. In some embodiments, thedisclosure further includes further comprising one or more empty memoryunits that are contiguously disposed in between the plurality of LMUsand the plurality of SMUs, and/or wherein the at least one processorfurther performs the steps of updating location data of the X3D memoryto indicate that the data stored in the first SMU has been relocated toa location of the memory unit adjacent to the last SMU, and updating thelocation data of the X3D memory to indicate that the data stored in thefirst LMU has been relocated to a location of the memory unit adjacentto the last LMU, and/or wherein the data of the first type is data thathas been accessed within a predetermined time period, and/or whereineach of the plurality of SMUs stores a portion of a flash translationlayer (FTL) table, and/or further comprising at least one empty memoryunit configured to temporarily store the data stored in the first LMUwhile the data in the first SMU is relocated to the memory unit adjacentto the last LMU, and/or further comprising at least one empty memoryunit configured to temporarily store the data stored in the first SMUwhile the data in the first LMU is relocated to the memory unit adjacentto the last SMU.

In another example embodiment, the disclosure includes a hybrid memorydevice (HMD), comprising, an X3D memory comprising a first plurality ofmemory units (MUs) and a second plurality of MUs, a processor coupled tothe X3D memory and configured to detect a trigger event that triggers aniteration of wear-leveling to be performed on the X3D memory, whereindata stored in a first MU of the first plurality of MUs is relocated toa MU adjacent to a last MU of the first plurality of MUs, wherein thefirst plurality of MUs are stored in contiguous locations in the X3Dmemory, wherein data stored in a first MU of the second plurality of MUsis relocated to a MU adjacent to a last MU of the second plurality ofMUs, and wherein the second plurality of MUs are stored in contiguouslocations in the X3D memory. In some embodiments, the disclosure furtherincludes further comprising a secondary memory coupled to the processorand the X3D memory, wherein the X3D memory comprises data of a firsttype, and wherein the secondary memory comprises data of a second type,and/or further comprising a temporary memory coupled to the processorand the X3D memory, wherein the temporary memory comprises at least oneof a location of the first MU of the first plurality of MUs, a locationof the last MU of the first plurality of MUs, a location of the first MUof the second plurality of MUs, and a location of the last MU of thesecond plurality of MUs, and/or wherein the location of the first MU ofthe first plurality of MUs is updated after the data stored in the firstMU of the first plurality of MUs is relocated to a memory unit adjacentto the last MU of the first plurality of MUs, and wherein the locationof the first MU of the second plurality of MUs is updated after the datastored in the first MU of the second plurality of MUs is relocated to amemory unit adjacent to the last MU of the second plurality of MUs,and/or wherein the X3D memory comprises at least one empty memory unit,wherein the data stored in the first MU of the first plurality of MUs iswritten to the empty memory unit, and wherein the data stored in thefirst MU of the second plurality of MUs is written to the memory unitwhere the first MU of the first plurality of MUs was located, and/orwherein the X3D memory comprises at least one empty memory unit, whereinthe data stored in the first MU of the second plurality of MUs iswritten to the empty memory unit, and wherein the data stored in thefirst MU of the first plurality of MUs is written to the memory unitwhere the first MU of the second plurality of MUs was located.

For the purpose of clarity, any one of the foregoing embodiments may becombined with any one or more of the other foregoing embodiments tocreate a new embodiment within the scope of the present disclosure.

These and other features will be more clearly understood from thefollowing detailed description taken in conjunction with theaccompanying drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of this disclosure, reference is nowmade to the following brief description, taken in connection with theaccompanying drawings and detailed description, wherein like referencenumerals represent like parts.

FIG. 1 illustrates an embodiment of an HMD that implements thewear-leveling embodiments described herein.

FIG. 2 illustrates an embodiment of an X3D memory.

FIG. 3 shows a method 300 for wear-leveling in an X3D memory.

FIGS. 4A and 4B illustrate representations of an initial state of an X3Dmemory before wear-leveling has been performed on the X3D memory.

FIGS. 5A and 5B illustrate representations of the X3D memory after afirst iteration wear-leveling has been performed on the X3D memory.

FIGS. 6A and 6B illustrate representations of the X3D memory after asecond iteration wear-leveling has been performed on the X3D memory.

FIGS. 7A and 7B illustrate representations of the X3D memory after athird iteration wear-leveling has been performed on the X3D memory.

FIGS. 8A and 8B illustrate representations of the X3D memory after afourth iteration wear-leveling has been performed on the X3D memory.

FIGS. 9A and 9B illustrate representations of the X3D memory after afifth iteration wear-leveling has been performed on the X3D memory.

FIGS. 10A and 10B illustrate representations of an initial state of X3Dmemory with an empty memory unit before wear-leveling has been performedon the X3D memory.

FIGS. 11A and 11B illustrate representations of an initial state of X3Dmemory with an empty memory unit after a first wear-leveling has beenperformed on the X3D memory.

FIGS. 12A and 12B illustrate representations of an initial state of X3Dmemory with an empty memory unit after a second wear-leveling has beenperformed on the X3D memory.

FIGS. 13A and 13B illustrate representations of X3D memory have multiplesections for storing various types of data.

DETAILED DESCRIPTION

It should be understood at the outset that although an illustrativeimplementation of one or more embodiments are provided below, thedisclosed systems and/or methods may be implemented using any number oftechniques, whether currently known or in existence. The disclosureshould in no way be limited to the illustrative implementations,drawings, and techniques illustrated below, including the exemplarydesigns and implementations illustrated and described herein, but may bemodified within the scope of the appended claims along with their fullscope of equivalents.

A conventional memory system on a mobile device includes variousdifferent types of memory that each stores different types of data basedon a frequency of access operations, such as reads and/or writes, thatare performed on the data. A mobile device typically includes a randomaccess memory (RAM), such as a dynamic RAM (DRAM) or a static RAM(SRAM), to store hot data. A hard drive, such as a solid-state drive ora hard disk drive, to store cold data. Some mobile devices may alsoinclude a flash memory, such as a NAND flash memory, to store warm data.Hot data generally refers to data for which access operations arecarried out on a relatively frequent basis. For example, an FTL table istypically considered hot data because the FTL tables needs to be writtento and updated frequently. Therefore, the FTL table is typically storedin a RAM of a mobile device because of the number of write cycles thatneeds to be performed on the FTL table. Warm data generally refers todata for which access operations are carried out on a less frequentbasis than hot data but on a more frequent basis than cold data. Forexample, user data that is frequently read but not frequently writtento, such as pictures or documents, may be considered warm data.Therefore, such pictures or documents are typically stored in a flashmemory of a mobile device when the mobile device includes a flashmemory. Cold data generally refers to data for which access operationsare rarely performed. For example, user data that is rarely read andnever updated, such as a document that a user read one time, may beconsidered cold data. Therefore, the document that is rarely accessed istypically stored in a hard drive of the mobile device. In oneembodiment, a mobile device may not include a flash memory. In such anembodiment, the hard drive would store both warm and cold data.

RAMs such as DRAM and SRAM are typically used to store hot data becauseRAM is fast. However, RAM is relatively expensive, especially at a largecapacities. RAM is also volatile in that data stored in the RAM iseventually lost when the RAM is not powered. Hard drives are orders ofmagnitude slower than RAM, but hard drives are very cheap and highcapacity. For this reason, a majority of user data is stored in harddrives. Flash memories that store warm data are cheaper than RAM andmuch faster than hard drives. These differences in performance,capacity, and cost between different types of memory devices forcemobile devices to have a restricted amount of hot data storage capacity,resulting in big performance penalties when the data the mobile deviceneeds is unavailable.

X3D technology and memory improves the storage of data by increasing adata access speed at which data stored in an X3D memory can be accessed.An X3D memory includes memory cells that can be directly accessedwithout having to read, erase, and program other memory cells. The X3Dtechnology thereby supports in-place-updating of memory in which newdata directly overrides old data at the location of the old data. Incontrast, RAM, such as DRAM, only supports out-of-place updating ofmemory in which new data has to be written in a new location and olddata has to be marked as out of date. Therefore, the data access speedin RAM is slower than X3D memory, and RAM requires more maintenance thanX3D memory. X3D technology currently does not implement a mechanism bywhich to differentiate between storing hot, warm, and cold dataaccording to the physical storage locations of hot, warm, and cold data.As such, X3D technology does not implement wear-leveling on the X3D.Wear-leveling operations should be performed on the X3D memory toprevent the X3D from wearing out and becoming unusable.

Disclosed herein are embodiments directed to an HMD that comprises anX3D memory partitioned into contiguous SMUs and contiguous LMUs. TheSMUs store hot data while the LMUs store warm and/or cold data. In anembodiment, the HMD is configured to perform wear-leveling on the SMUsand the LMUs by relocating data of a first SMU to a memory unit adjacentto a last SMU of the contiguous SMUs and relocating data of a first LMUto a memory unit adjacent to a last LMU of the contiguous LMUs.Wear-leveling is applied to the SMUs and LMUs to maintain asubstantially equal write frequency across all memory units. This way,each SMU and LMU wears out at substantially the same rate. Embodimentsof wear-leveling disclosed herein maintain the sequential order of datastructure stored in the SMUs and LMUs. Wear-leveling is implemented in amanner such that all SMUs remain contiguous with each other, and allLMUs remain contiguous with each other after each iteration ofwear-leveling.

FIG. 1 illustrates an embodiment of HMD 100 that implements thewear-leveling embodiments described herein. HMD 100 comprisesinput/output (I/O) ports 110, transceiver units (Tx/Rx) 120, a processor130, an X3D memory 133, a secondary memory 140, and a temporary memory150. Ports 110 are coupled to Tx/Rx 120, which may be transmitters,receivers, or combinations thereof The Tx/Rx 120 may transmit andreceive data via the ports 110. Processor 130 is configured to processdata. X3D memory 133, secondary memory 140, and/or temporary memory 150may be configured to store data and instructions for implementingembodiments described herein. The HMD 100 may also compriseelectrical-to-optical (EO) components and optical-to-electrical (OE)components coupled to the ports 110 and Tx/Rx 120 for receiving andtransmitting electrical signals and optical signals.

The processor 130 may be implemented by hardware, software, and/orfirmware. The processor 130 may be implemented as one or more centralprocessing unit (CPU) chips, logic units, cores (e.g., as a multi-coreprocessor), field-programmable gate arrays (FPGAs), application specificintegrated circuits (ASICs), and digital signal processors (DSPs). Theprocessor 130 is in communication with the ports 110, Tx/Rx 120, X3Dmemory 133, secondary memory 140, and temporary memory 150.

The processor 130 comprises a wear-leveling module 153. The processor130 may be configured to implement the wear-leveling module 153 toexecute the instructions for implementing various embodiments disclosedherein. In an embodiment, the wear-leveling module 153 may beimplemented as instructions stored in one or more of the X3D memory 133,secondary memory 140, and/or temporary memory 156. The processor 130 mayalso implement method 300 discussed herein. The inclusion of thewear-leveling module 153 and the storage location module 156 provide animprovement to the functionality of HMD 100. The wear-leveling module153 and the storage location module 156 also effect a transformation ofHMD 100 to a different state.

The X3D memory 133 is structured and functions according to U.S. Pat.No. 8,416,609 ('609 Patent), issued Apr. 9, 2013, which is herebyincorporated by reference. In an embodiment, the X3D memory may beformed by slicing sub-microscopic layers of materials into columns. Eachcolumn contains a memory cell and a selector. The columns are connectedin a structure consisting of perpendicular wires that enables the memorycells to individually address by selecting one wire on top and anotherwire at the bottom of the memory cell. The structure can be stackedthree-dimensionally to maximize density. Each memory cell can be writtento or read by variating a voltage sent to the respective selector of thememory cell. X3D technology is a simple, stackable, transistor-lessdesign that enables a storage capacity of up to ten times more thanDRAM. In addition, data stored in the X3D is more non-volatile in thatdata is not lost upon power off.

According to some embodiments, the X3D memory 133 is divided into twosections. The first section includes SMUs 161, and the second section isLMUs 164. The SMUs 161 are stored in contiguous locations of the X3Dmemory 133, and the LMUs 164 are stored in contiguous locations of theX3D memory 133. Contiguous as referred to herein means adjoining,sharing a common border, touching, next to, or together in sequence. Inan embodiment, each of the SMUs 161 is configured to store hot data 185,and each of the LMUs 164 are configured store warm/cold user data 188.Hot data 185 comprises hot data, such as the FTL table. Warm/cold userdata 188 comprises warm data that are more frequently accessed than theuser data 167 stored in the secondary memory 140.

In an embodiment, the processor 130 is configured to dynamicallyallocate a certain portion of the X3D memory as SMUs 161 and anotherportion of the X3D as LMUs 164. In an embodiment, the processor isconfigured to dynamically update the size of SMUs 161 and/or the LMUs164 as needed. For example, suppose the FTL table is stored at SMUs 161,and the size of the FTL table becomes too large to be supported by thecurrent size of the SMUs 161. When there is empty storage space in theLMUs 164 that can be converted to an SMU 161, the processor 130 may beconfigured to dynamically configure one or more of the empty LMUs 164 tobe SMUs 161. In this way, SMUs 161 can be expanded by allocating theempty LMUs 164 as instead being SMUs 161 to store the remainder of theFTL table.

The secondary memory 140 comprises a flash drive, such as a NAND flashmemory. In an embodiment, the secondary memory 140 is configured tostore user data 167, which is cold data that is relatively colder (i.e.,less frequently accessed) than the data stored at SMUs 161 and LMUs 164.In an embodiment, the processor 130 may be configured to determinewhether to write data to the X3D memory 133 or the secondary memory 140based on an estimated frequency of access of the data. For example, if auser is trying to save a document to the HMD, and the document isestimated to be a document that the user will likely never access again,the storage location module 156 will store the document in user data 167instead of warm/cold user data 188 or hot data 185.

Temporary memory 150 may be one or more disks, tape drives, orsolid-state drives and may be used to store SMU description data 170,LMU description data 173, and location data 174. Temporary memory 150may be volatile and non-volatile and may be read-only memory (ROM), RAM,ternary content-addressable memory (TCAM), a DRAM, and SRAM. SMUdescription data 170 comprises data describing a size of the SMUs 161,an accessible size of the SMUs 161, a wear-leveling size of the SMUs161, locations of the SMUs 161, and/or identifications of data stored atthe SMUs 161. The size of the SMUs 161 may indicate in bytes (B) a sizeof SMUs 161 is in the X3D memory 133. The accessible size of the SMUs161 indicates a smallest read/write accessible area of the SMUs 161. Forexample, the read/write accessible size of the SMUs 161 may be 64 Bbecause 64 bytes of the SMUs 161 may need to be accessed at one time toperform a read and/or write operation. The wear-leveling size of theSMUs 161 indicates a smallest accessible area of the SMUs 161 forpurposes of wear-leveling. For example, the wear-leveling size of theSMUs 161 may be 4 kB because 4 kB of the SMUs 161 may need to beaccessed at one time to perform a wear-leveling operation, as disclosedherein. The locations of the SMUs 161 may indicate location identifiersfor the memory cells in the SMUs 161. The identifications of data storedat the SMUs 161 may identify data that is stored in the SMUs 161.

LMU description data 173 comprises data describing a size of the LMUs164, an accessible size of the LMUs 164, a wear-leveling size of theLMUs 164, locations of the LMUs 164, and/or identifications of datastored at the LMUs 164. The size of the LMUs 164 may indicate a size ofthe LMUs4 164 in B. The accessible size of the LMUs 164 indicates asmallest read/write accessible area of the LMUs 164. For example, theread/write accessible size of the LMUs 164 may be 4 kB because 4 kB ofthe LMUs 164 may need to be accessed at one time to perform a readand/or write operation. The wear-leveling size of the LMUs 164 indicatesa smallest accessible area of the LMUs 164 for purposes ofwear-leveling. For example, the wear-leveling size of the LMUs 164 maybe 4 kB because 4 kB of the LMUs 164 may need to be accessed, at onetime, to perform a wear-leveling operation, as disclosed herein. Thelocations of the LMUs 164 may indicate location identifiers for thememory cells in the LMUs 164. The identifications of data stored at theLMUs 164 may identify data that is stored in the LMUs 164.

Location data 174 includes locations of data segments stored at one ormore of the SMUs 161 and/or the LMUs 164. For example, location data 174includes one or more locations of memory cells or groups of memory cellsthat store one or more data segments of a file. In an embodiment,location data 174 only stores location information for the memory cell,SMU 161, or LMU 164 storing the first data segment of an ordered file.For example, suppose a movie file contains eleven data segments storedsequentially and contiguously in LMUs 164. In this case, location data174 may only store the location of the LMU 164 storing the first of theeleven data segments of the movie file. In an embodiment, location data174 stores location information for each of the eleven data segments ofthe movie file. As another illustrative example, suppose the FTL table,which is an ordered table, includes 200 segments stored in contiguousSMUs 161. In this case, location data 174 may only store the location ofthe SMU 171 storing the first of the 200 segments of the FTL table. Inan embodiment, location data 174 stores location information for each ofthe 200 segments of the FTL table.

In an embodiment, SMU description data 170, LMU description data 173,and location data 174 may be stored in one or more of either the X3Dmemory 133, secondary memory 140, and/or temporary memory 150. HMD 100may include other means for implementing the wear-leveling module 153and/or method 300 selected for execution, and to store instructions anddata that are read during program execution.

In an embodiment, wear-leveling is performed on the X3D memory 133across both SMUs 161 and LMUs 164. In an iteration of wear-leveling,data stored at a first SMU 161 is relocated to a memory unit after alast SMU 161, and data stored at a first LMU 164 is relocated to amemory unit after a last LMU 164. The switching of hot and cold dataresults in the first SMU 161 switching physical locations with the firstLMU 164 in the X3D memory 133. Since the SMUs 161 store hot data and theLMUs 164 store cold data, the wear-leveling process results in theswitching of hot and cold data. This helps to ensure that the locationsin X3D memory 133 that store hot and the locations in X3D memory 133that store cold data are accessed at a substantially equal frequencythroughout the lifetime of the X3D memory 133. Such a method ofwear-leveling maintains the order of data structures stored in SMUs 161and LMUs 164. While each iteration of wear-leveling changes the absolutelocations of data, the relative locations of ordered data in the SMUs161 and the LMUs 164. In addition, the methods of wear-levelingdisclosed herein maintain the contiguous nature of the SMUs 161 and theLMUs 164.

In an embodiment, X3D memory 133 includes one or more empty memoryunits. An empty memory unit does not store any data and may not beconfigured as either an SMU or an LMU. In an embodiment, the emptymemory units may be configured as either an SMU or an LMU but still doesnot store data. In an iteration of wear-leveling on an X3D memory 133with one or more empty memory units, either a first SMU 161 or a firstLMU 164 is relocated to the empty memory unit. Then the empty memory isrelocated to the location of either either the first SMU 161 or thefirst LMU 164. The empty memory unit is involved in the wear-levelingprocess as data is written to and from the empty memory to another SMUor LMU during each iteration of wear-leveling.

To facilitate the relocation process of wear-leveling, the X3D memory133 can comprise an empty buffer after each memory unit section, whichis reserved for the write operation when swapping memory units. It isunderstood that by programming and/or loading executable instructionsonto the HMD 100, at least one of the processor 130, X3D memory 133,secondary memory 140, and/or temporary memory 150 are changed,transforming the HMD 100 in part into a particular machine or apparatus,e.g., a multi-core forwarding architecture, having the novelfunctionality taught by the present disclosure. It is fundamental to theelectrical engineering and software engineering arts that functionalitythat can be implemented by loading executable software into a computercan be converted to a hardware implementation by well-known designrules. Decisions between implementing a concept in software versushardware typically hinge on considerations of stability of the designand numbers of units to be produced rather than any issues involved intranslating from the software domain to the hardware domain. Generally,a design that is still subject to frequent change may be preferred to beimplemented in software, because re-spinning a hardware implementationis more expensive than re-spinning a software design. Generally, adesign that is stable and that will be produced in large volume may bepreferred to be implemented in hardware, for example in an ASIC, becausefor large production runs the hardware implementation may be lessexpensive than the software implementation. Often a design may bedeveloped and tested in a software form and later transformed, bywell-known design rules, to an equivalent hardware implementation in anASIC that hardwires the instructions of the software. In the same manneras a machine controlled by a new ASIC is a particular machine orapparatus, likewise a computer that has been programmed and/or loadedwith executable instructions (e.g., a computer program product stored ina non-transitory medium/memory) may be viewed as a particular machine orapparatus.

FIG. 2 illustrates an embodiment of an X3D memory 200. In an embodiment,the X3D memory 200 is similar to X3D memory 133. As shown in FIG. 2 ,X3D memory 200 comprises a section 203 for SMUs and a section 206 forLMUs. The section 203 for SMUs comprises a plurality of SMUs 210, suchas SMUs 161. The section 206 for LMUs comprises a plurality of LMUs 215,such as LMUs 164. As shown in FIG. 2 , the SMUs 210 are stored incontiguous locations of section 203 for SMUs 210 in the X3D memory 200.Similarly, the LMUs 164 are stored in contiguous locations of section206 for LMUs 215 in the X3D memory 200. The SMUs 210 are contiguous withone another such that each SMU 210 is adjacent to at least one other SMU210. The LMUs 215 are contiguous with one another such that each LMU 215is adjacent to at least one other LMU 215. In an embodiment, the section203 for SMUs 210 is also contiguous with the section 206 for LMUs 215such that there are no empty memory units between the last SMU 210 andthe first LMU 215. In an embodiment, there may be one or more emptymemory units between the last SMU 210 and the first SMU 215.

In an embodiment, a smallest accessible unit in an X3D memory is 16 B.The SMUs 210 may be configured such that a smallest accessible unit forread and/or write purposes is 64 B, or any other multiple of 16 B. TheLMUs 215 may be configured such that a smallest accessible unit for readand/or write purposes is 4 kB, or any other multiple of 4 kB. The SMUs210 may be configured such that a smallest accessible unit forwear-leveling purposes is 4 kB, or any other multiple of 4 kB.Similarly, the LMUs 215 may be configured such that a smallestaccessible unit for wear-leveling purposes is 4 kB, or any othermultiple of 4 kB. In an embodiment, the smallest accessible unit forwear-leveling purposes should be the same for SMUs 210 and LMUs 215 sothe wear-leveling is performed evenly. For example, the SMU 210 storesthe FTL table and other frequently accessed data, and the LMU storesuser data and other less frequently accessed data. For improvingwear-leveling processes, the FTL table entries in the SMU 210 can becombined into larger groups to be the same size as an LMU (4 kB). TheX3D 200 shown in FIG. 2 only includes SMUs 210 and LMUs 215. However, itshould be appreciated that X3D 200 may otherwise include other types ofmemory units or may have memory units or cells that are left blank andunassigned to a specific type of memory unit.

While X3D memory 200 only shows section 203 for SMUs and section 206 forLMUs, X3D memory 200 may also include a section for one or more MMUs orempty memory units. The MMUs are memory units configured to store warmdata. MMUs may be contiguous with each other and may be located beforethe SMUs, between the SMUs and the LMUs, or after the LMUs. The emptymemory units are memory units that are not particularly configured tostore hot, cold, or warm data, and do not store data. The empty memoryunits may also be contiguous with each other and located before theSMUs, between the SMUs and the LMUs, or after the LMUs. X3D memory mayalso include any number of sections for SMUs, LMUs, MMUs, or emptymemory units. For example, X3D memory 200 may include two sections forSMUs, 1 section for MMUs, 3 sections for LMUs, and 2 sections for emptymemory units. Therefore, X3D memory 200 may be configured to storevarious types of data (e.g., temperatures of data) so long as the memoryunits that store a particular type of data are in a logically contiguousarea of the memory. Embodiments of the present disclosure are directedto wear-leveling between the various sections of memory units whilemaintaining data structures and the order of data intact aswear-leveling is performed.

While X3D memory 200 shows that the section 203 for SMUs is smaller thanthe section 206 for LMUs, it should be appreciated that section 203 forSMUs may be larger than or the same size as section 206 for LMUs. An X3Dmemory 200 may include any number of memory units to store hot, warm,and cold data. The size of section of the sections that store SMUs,MMUs, and LMUs may vary.

FIG. 3 shows a method 300 for wear-leveling in an X3D memory. The method300 for wear-leveling in an X3D memory may be implemented when a triggerevent is detected or upon a pre-determined schedule. In an embodiment,the X3D is similar to X3D 200. At block 305, a trigger event forinitiating an iteration of a wear-leveling process on the X3D isdetected. For example, the processor 130 detects the trigger event. TheX3D memory comprises a first section of memory units and a secondsection of memory units. The first section of memory units and thesecond section of memory units may be SMUs, LMUs, or MMUs. The firstsection of memory units comprises a plurality of contiguous memory unitsconfigured to store data of a first type, and the second section ofmemory units comprises a plurality of memory units configured store dataof a second type. In an embodiment, the various types of data may be hotdata, warm data, and cold data. The trigger event for initiating aniteration of the wear-leveling process on the X3D can occur when a fixedfrequency of accesses to one or more of the plurality of SMUs reaches apre-determined threshold. For example, the wear-leveling process may betriggered after a number of write operations on one of the SMUs/LMUs, orthe whole SMU/LMU contiguous memory area has exceeded the pre-determinedthreshold. In an embodiment, the trigger event may be based on a dynamicequation factoring in a number of operations, environmental factors,preset durations, and the like. In an embodiment, the trigger event maybe based on a wear-leveling schedule that has been pre-configured andstored in an HMD such that an iteration of the wear-leveling processbegins according to the wear-leveling schedule.

At block 310, data stored in a first memory unit of the first section ofmemory units is relocated to a memory unit adjacent to a last memoryunit of the first section of memory units. For example, data stored in afirst SMU of a plurality of SMUs is relocated to a memory unit adjacentto the last SMU of the plurality of SMUs. For example, the processor 130may configure the X3D memory 133 to relocate data stored in a first SMUof SMUs 161 to a memory unit adjacent to the last SMU of SMUs 161. TheSMUs are stored in contiguous locations in an X3D memory. At block 315,data stored in a first memory unit of the second section of memory unitsis relocated to a memory unit adjacent to a last memory unit of thesecond section of memory units. For example, data stored in a first LMUof a plurality of LMUs is relocated to a memory unit adjacent to a lastLMU of the LMUs. For example, the processor 130 may configure the X3Dmemory 133 to relocate cold data stored in the first LMU of the LMUs 164to a memory unit adjacent to the last LMU of the LMUs 164. The LMUs arealso stored in contiguous locations in the X3D memory.

In an embodiment, wear-leveling is performed on an X3D memory byrelocating data on an SMU to a memory unit that is immediately after thelast SMU in a clockwise manner. Suppose the size of the SMU, or thenumber of actual SMUs in the X3D memory, is represented by S(SMU), andthe size of the LMU, or the number of actual LMUs in the X3D memory, isrepresented by S(LMU). For example, if there are 5 SMUs, then S(SMU) is5. In this case where S(SMU)=5, a first iteration of wear-levelingperformed on the SMU relocates data stored in the first SMU to thememory unit right after the fifth SMU. When the memory unit immediatelyafter the fifth SMU is the first LMU, then the data stored at the firstLMU may be temporarily written to a buffer memory while the data storedat the first SMU is written to the location of the first LMU. When thememory unit immediately after the fifth SMU is an empty memory unit,then the data previously stored at the first SMU may be written to thelocation of the empty memory unit. Therefore, wear-leveling is performedby moving data from an SMU to S(SMU) memory units ahead. In other words,a memory unit at the beginning of the contiguous location is moved tothe end of the contiguous location. This method maintains the same typeof unit in a contiguous location, but shifts the overall location overone unit space while shifting the order of the units.

The LMU must also be shifted over to the memory unit right after thelast LMU. In terms of timing, the SMU can be relocated before thecorresponding LMU, or vice versa. In this way, the wear-leveling processdisclosed herein switches the storing of hot data and cold data (thecold data may include warm data as well) on different locations of theX3D. Switching storage locations of hot and cold data helps ensure thatall of the memory units in an X3D memory are accessed a substantiallyequal number of times, thus preventing some memory units fromdeteriorating before other memory units. In various embodiments, thememory unit storing critical data may receive relocation priority in theprocess. Furthermore, the wear-leveling process can occur in thebackground of the mobile device operations during idle times, or, insome instances, be performed in the foreground of the operations.

FIGS. 4A to 4B illustrate representations of an initial state of an X3Dmemory 400 before wear-leveling has been performed on the X3D memory400. FIG. 4A shows a grid representation of the initial state of the X3Dmemory 400. X3D memory 400 is similar to X3D memory 200, except the gridrepresentation of X3D memory 400 includes only one row (or section) 450of memory units configured as SMUs and one row 455 of memory unitsconfigured as LMUs are shown. As should be appreciated, any number ofmemory units may be configured as SMUs and/or LMUs in X3D memory 400, aslong as the SMUs are contiguous with one another and the LMUs arecontiguous with one another.

Row 450 includes an array of memory units that are each configuredsequentially as SMUs 401 to 405. In an embodiment, SMUs 401 to 405 areeach similar to SMU 210. As shown in FIG. 4A, SMUs 401 to 405 eachrespectively stores data segments 1 to 5 of a file. SMU 401 stores datasegment 1, SMU 402 stores data segment 2, SMU 403 stores data segment 3,SMU 404 stores data segment 4, and SMU 405 stores data segment 5. Forexample, data segments 1 to 5 represent sequential data segments of anordered FTL table (hot data). Row 450 also includes an array of emptymemory units that are each configured as SMUs 430 to 437. In anembodiment, SMUs 430 to 437 are similar to SMU 210 and do not store anydata. As should be appreciated, X3D memory 400 may include any number ofSMUs so long as they are arranged in a contiguous manner.

Row 455 includes the array of memory units that are each configuredsequentially as LMUs 406 to 416. In an embodiment, LMUs 406 to 416 aresimilar to LMU 215. As shown in FIG. 4A, LMUs 406 to 416 eachrespectively stores data segments 11 to 21 of a file. LMU 406 storesdata segment 11, LMU 407 stores data segment 12, LMU 408 stores datasegment 13, LMU 409 stores data segment 14, LMU 410 stores data segment15, LMU 411 stores data segment 16, LMU 412 stores data segment 17, LMU413 stores data segment 18, LMU 414 stores data segment 19, LMU 415stores data segment 20, and LMU 416 stores data segment 21. For example,data segments 11 to 21 represent sequential data segments of a moviefile. Row 455 also includes an array of empty memory units that are eachconfigured as LMUs 438 to 439. In an embodiment, LMUs 438 to 439 aresimilar to LMU 215 and do not store any data. As should be appreciated,X3D memory 400 may include any number of SMUs so long as they arearranged in a contiguous manner.

As shown in FIG. 4A, row of 450 includes the array of memory unitsconfigured as SMUs 401 to 405 that respectively store data segments 1 to5 and empty SMUs 430 to 437. Row 455 includes the array of memory unitsconfigured as LMUs 406 to 416 that respectively store data segments 11to 21 and empty LMUs 438 to 439. SMUs 401 to 405 and SMUs 430 to 437 arecontiguous with each other such that they are adjacent to one another inrow 450, and there are no LMUs interleaved between any of the SMUs.Similarly, LMUs 406 to 416 and LMUs 438 to 439 are contiguous with eachother such that they are adjacent to one another in row 455, and thereare no SMUs interleaved between any of the LMUs. In an embodiment, thefirst iteration of wear-leveling comprises relocating the first SMU(e.g., SMU 401) to a memory unit after a last empty SMU (e.g., SMU 437)and relocating the first LMU 406 to a memory unit after the last emptyLMU (e.g., LMU 439).

FIG. 4B shows a circular representation of the initial state of the X3Dmemory 400 with arrow 480 illustrating how a first iteration ofwear-leveling will be performed on the X3D memory 400. The circularrepresentation of X3D memory 400 shown in FIG. 4B is structured similarto and stores similar data segments as the grid representation of X3Dmemory 400 shown in FIG. 4A.

As indicated by arrow 480, the first iteration of wear-levelingcomprises relocating a first SMU (e.g., SMU 401) to a memory unit aftera last SMU (e.g. SMU 405) and relocating a first LMU (e.g., LMU 406) toa memory unit after the last LMU (e.g., LMU 416). X3D memory 400 shownin FIG. 4B does not include any empty SMUs or empty LMUs (although X3Dmemory 400 shown in FIG. 4A does). However, the last contiguous SMU isconsidered the last SMU, regardless of whether the SMU stores data ornot. Similarly, the last contiguous LMU is considered the last LMU,regardless of whether the LMU stores data or not. Therefore, althoughFIG. 4B shows that data is to be moved from SMU 401 to a memory unitafter SMU 405, the data may be actually moved to a memory unit after thelast SMU of the plurality of contiguous SMUs regardless of whether theSMU stores data or not. Similarly, while FIG. 4B shows data to be movedfrom LMU 406 to a memory unit after LMU, the data may be actually movedto a memory unit after the last LMU of the plurality of contiguous LMUsregardless of whether the LMU stores data or not.

For example, relocating SMU 401 to a memory unit after SMU 405 compriseswriting the data segment 1 to a temporary buffer, and then erasing datasegment 1 from the location of SMU 401. Once data segment 1 is erasedfrom the location of SMU 401, the previous location of SMU 401 becomesan empty memory unit. Data segment 11 may then be written from LMU 406to the empty memory unit. Once the data segment 11 is written to emptymemory unit, data segment 11 may be erased from LMU 406 such that thelocation of LMU 406 also becomes another empty memory unit. Data segment1 may then be written from the temporary buffer to the empty memory unitwhere LMU 406 was previously located.

As another illustrative example in which there are one or more emptymemory units already present in X3D memory between LMU 416 and SMU 401,wear-leveling may be performed without the use of a temporary buffer.First, data segment 11 may be written from LMU 406 to the empty memoryunit, such that the previous location of LMU 406 becomes an empty memoryunit. Then, data segment 1 from SMU 401 may be written from SMU 401 tothe empty memory unit where LMU 406 was previously located. Data segment1 may be erased from SMU 401 such that there is still an empty memoryunit between the SMUs and the LMUs in the X3D memory 400 after a firstiteration of wear-leveling.

Such an embodiment of wear-leveling amounts to switching the location ofthe first SMU 401 with the location of the first LMU 406. Arrow 480points to SMU 401 and LMU 406, which will both be relocated during thefirst iteration of wear-leveling. After the first iteration ofwear-leveling, the locations of SMU 401, storing hot data segment 1, andLMU 406, storing warm/cold data segment 11, will be swapped in X3Dmemory 400. Therefore, the embodiments of wear-leveling disclosed hereinthat switch locations of SMU 401 and LMU 406 facilitate ensuring thatthe locations of SMU 401 and LMU 406 are accessed at a similar frequencythroughout the lifetime of X3D memory 400. In an embodiment, locationdata (e.g., location data 174) associated with the SMUs and LMUs may beupdated to reflect the first iteration of wear-leveling. For example,the new locations of SMU 401 and/or LMU 406 may be updated after thefirst iteration of wear-leveling is complete.

FIGS. 5A and 5B illustrate representations of an X3D memory 500 afterthe first iteration of wear-leveling has been performed on the X3Dmemory 400. FIG. 5A shows a grid representation of the X3D memory 500.The grid representation of X3D memory 500 is structured similar to thegrid representation of X3D memory 400, except that in X3D memory 500,the memory unit that stores data segment 1 (e.g., SMU 501) and thememory unit that stores data segment 11 (e.g., SMU 506) have switchedlocations.

Row 550 includes an array of memory units that each configuredsequentially as SMUs 502, 503, 504, 505, and 501. SMUs 501 to 505 aresimilar to SMUs 401 to 405 and store similar data segments,respectively, except the absolute location of SMU 501 has changed. Row(or section) 555 also includes an array of memory units that are eachconfigured sequentially as LMUs 507, 508, 509, 510, 511, 512, 513, 514,515, 516, and 506. LMUs 506 to 516 are similar to LMUs 406 to 416 andstore similar data segments, respectively, except the absolute locationof SMU 506 has changed. As shown in FIG. 5 , row 550 may include anyadditional number of empty SMUs, and row 555 may include any additionalnumber of empty LMUs.

After the first iteration of wear-leveling is performed on X3D memory400 to result in X3D memory 500, the first memory unit in row 550 is nowconfigured as LMU 406 storing data segment 11 (warm/cold data).Similarly, the first memory unit in row 555 is now configured as SMU 501storing data segment 1 (hot data). In effect, the first iteration ofwear-leveling has swapped the locations of SMU 401 and LMU 406 to resultin the post wear-leveling locations of SMU 501 and SMU 506. Theswitching of locations of SMU 401 with LMU 406 results in the swappingof storage locations of hot data and warm/cold data. This swapping ofstorage locations of hot data and cold data serves to prevent memorycells associated with storing hot data from deteriorating (or wearingout) faster memory cells associated with storing cold data deteriorate.In this way, the wear-leveling schemes disclosed herein provide for away to configure an X3D memory 500 to maintain a substantially equalread and write frequency across all memory units, both SMUs and LMUs.

FIG. 5B shows a circular representation of the X3D memory 500 after thefirst iteration of wear-leveling has been performed on the X3D memory400 with arrow 580 illustrating how a second iteration of wear-levelingwill be performed on the X3D memory 500. The circular representation ofX3D memory 500 shown in FIG. 5B is structured similar to and storessimilar data segments as the grid representation of X3D memory 500 shownin FIG. 5A, except that in X3D memory 500, the memory unit that storesdata segment 1 (e.g., SMU 501) and the memory unit that stores datasegment 11 (e.g., SMU 506) have switched locations. As shown in FIG. 5B,SMUs 502-505 remain in their original memory unit locations, while SMU501 has moved from the beginning of the array of SMUs to the end of thearray of SMUs. Similarly, LMUs 507 to 516 remain in their originalmemory unit locations, while LMU 506 has moved from the beginning of thearray of LMUs to the end of the array of LMUs.

After the first iteration of wear-leveling has been performed to createX3D memory 500, the array of memory units configured as SMUs remaincontiguous to each other in that the SMUs are still adjacent to eachother without any interleaving LMUs. Similarly, the array of memoryunits configured as LMUs also remain contiguous to each other in thatthe LMUs are still adjacent to each other without any interleaving SMUs.

The change in absolute locations (as shown in FIG. 5A) does not alterthe relative locations of the SMUs and LMUs in a circular fashionbecause SMUs and LMUs are not interleaved in between each other. Theorder of the data segments stored in the array of SMUs are maintainedrelative to the locations of the other SMUs in a circular fashion. Forexample, the order of the data segments stored at the SMUs is now 2, 3,4, 5, and 1. When the HMD knows the location of data segment 1, the HMDknows that the remaining SMUs store the remainder of data segments 1-5sequentially in a circular fashion since all SMUs are contiguous, andthe order of the SMUs storing the sequential data segments has not beendisrupted. In an embodiment, a processor (e.g., processor 130) coupledto X3D memory 500 may be configured to update a location data (e.g.,location data 174) each time an iteration of wear-leveling has beenperformed on the X3D memory 500. For example, before the first iterationof wear-leveling has been performed on X3D memory 500, the location dataindicated that the location of SMU 401 was the location of the memoryunit after the last LMU 416. After the first iteration of wear-levelinghas been performed on X3D memory 500, the processor updates the locationdata to indicate that the location of SMU 501 is the memory unit afterSMU 505. In this way, the location of the first SMU, last SMU, firstLMU, and/or last LMU may be stored and later searched for. For example,the processor may search the location data to identify the location ofSMU 501 as the location of data segment 1, and circle around to the nextSMU to find the remaining sequence of data segments 2-5. Accordingly,the wear-leveling methods and systems described herein maintain theorder of the data structure stored in data segments 1-5. A similarmechanism can be used to update the location data of data segments 11-21stored at LMUs 506 to 516.

As indicated by arrow 580, a second iteration of wear-leveling comprisesrelocating a first SMU (e.g., SMU 502) to a memory unit after a last SMU(e.g. SMU 501) and relocating a first LMU (e.g., LMU 507) to a memoryunit after the last LMU (e.g., LMU 506). Such an embodiment ofwear-leveling amounts to switching the location of the first SMU 502with the location of the first LMU 507. Arrow 580 points to SMU 502 andLMU 507 in X3D memory 500 that will be relocated during the seconditeration of wear-leveling. After the second iteration of wear-leveling,the locations of SMU 502, storing hot data segment 2, and LMU 507,storing warm/cold data segment 12, will be swapped in X3D memory 500.Therefore, the embodiments of wear-leveling disclosed herein that switchlocations of SMU 502 and LMU 507 facilitate ensuring that the locationsof SMU 502 and LMU 507 are accessed at a similar frequency throughoutthe lifetime of X3D memory 500. In an embodiment, location data (e.g.,location data 174) associated with the SMUs and LMUs may be updated toreflect the second iteration of wear-leveling. For example, the newlocations of SMU 502 and/or LMU 507 may be updated after the seconditeration of wear-leveling is complete.

FIGS. 6A and 6B illustrate representations of an X3D memory 600 after asecond iteration of wear-leveling has been performed on the X3D memory400. FIG. 6A shows a grid representation of the X3D memory 600. The gridrepresentation of X3D memory 600 is similar to the grid representationof X3D memory 500, except that in X3D memory 500, the memory unit thatstores data segment 2 (e.g., SMU 602) and the memory unit that storesdata segment 12 (e.g., SMU 607) have switched locations.

X3D memory 600 includes an array of memory units that each configuredsequentially as SMUs 603, 604, 605, 601, and 602. SMUs 601 to 605 aresimilar to SMUs 501 to 505 and store similar data segments,respectively, except that the absolute location of SMU 602 has changed.X3D memory 600 also includes an array of memory units that are eachconfigured sequentially as LMUs 608, 609, 610, 611, 612, 613, 614, 615,616, 606, and 607. LMUs 606 to 616 are similar to LMUs 506 to 516 andstore similar data segments, respectively, except that the absolutelocation of LMU 607 has changed. As shown in FIG. 6 , row (or section)650 may include any additional number of empty SMUs, and row 655 mayinclude any additional number of empty LMUs.

After the next iteration of wear-leveling is performed on X3D memory 500to result in X3D memory 600, the second memory unit in row 650 is nowconfigured as LMU 607 storing data segment 12 (warm/cold data).Similarly, the second memory unit in row 655 is now configured as SMU602 storing data segment 2 (hot data). In effect, the second iterationof wear-leveling swaps the locations of SMU 402 and LMU 407 (see FIG. 4) to result in the post wear-leveling locations of SMU 602 and SMU 607.

FIG. 6B shows a circular representation of the X3D memory 600 afteranother iteration of wear-leveling has been performed on the X3D memory500 with an arrow 680 illustrating how a third iteration ofwear-leveling will be performed in X3D memory 600. The circularrepresentation of X3D memory 600 shown in FIG. 6B is structured similarto and stores similar data segments as the circular representation ofX3D memory 600 shown in FIG. 6A, except that in X3D memory 600, thememory unit that stores data segment 2 (e.g., SMU 602) and the memoryunit that stores data segment 12 (e.g., SMU 607) have switchedlocations.

As shown in FIG. 6B, SMUs 603-605 remain in their original memory unitlocations, and SMU 601 remains moved from the beginning of the array ofSMUs to the end of the array of SMUs. However, SMU 602 has moved fromthe beginning of the array of SMUs to the end of the array of SMUs. Theorder of the array of memory units configured as SMUs becomes SMU 603,SMU 604, SMU 605, SMU 601, and SMU 602. Similarly, LMUs 608 to 616remain in their original memory unit locations, and LMU 606 remainsmoved from the beginning of the array of LMUs to the end of the array ofLMUs. However, SMU 607 has moved from the beginning of the array of LMUsto the end of the array of LMUs.

After the second iteration of wear-leveling has been performed to createX3D memory 600, the array of memory units configured as SMUs remaincontiguous to each other in that the SMUs are still adjacent to eachother without any interleaving LMUs. Similarly, the array of memoryunits configured as LMUs also remain contiguous to each other in thatthe LMUs are still adjacent to each other without any interleaving SMUs.The order of the data segments stored in the array of SMUs and LMUs arealso maintained relative to the locations of the other SMUs in acircular fashion.

As indicated by arrow 680, a third iteration of wear-leveling comprisesrelocating a first SMU (e.g., SMU 603) to a memory unit after a last SMU(e.g. SMU 602) and relocating a first LMU (e.g., LMU 608) to a memoryunit after the last LMU (e.g., LMU 607). Such an embodiment ofwear-leveling amounts to switching the location of the first SMU 603with the location of the first LMU 608. Arrow 680 points to SMU 603 andLMU 608 in X3D memory 600 that will be relocated during the thirditeration of wear-leveling. After the third iteration of wear-leveling,the locations of SMU 603, storing hot data segment 3, and LMU 608,storing warm/cold data segment 13, will be swapped in X3D memory 600.Therefore, the embodiments of wear-leveling disclosed herein that switchlocations of SMU 603 and LMU 608 facilitate ensuring that the locationsof SMU 603 and LMU 608 are accessed at a similar frequency throughoutthe lifetime of X3D memory 600. In an embodiment, location data (e.g.,location data 174) associated with the SMUs and LMUs may be updated toreflect the third iteration of wear-leveling. For example, the newlocations of SMU 603 and/or LMU 608 may be updated after the thirditeration of wear-leveling is complete.

FIGS. 7A and 7B illustrate representations of an X3D memory 700 after athird iteration of wear-leveling has been performed on the X3D memory400. FIG. 7A shows a grid representation of the X3D memory 700 afteranother iteration of wear-leveling has been performed on the X3D memory600. The grid representation of X3D memory 700 is similar to the gridrepresentation of X3D memory 600, except that in X3D memory 700, thememory unit that stores data segment 3 (e.g., SMU 703) and the memoryunit that stores data segment 13 (e.g., SMU 708) have switchedlocations.

X3D memory 700 includes an array of memory units that each configuredsequentially as SMUs 704, 705, 701, 702, and 703. SMUs 701 to 705 aresimilar to SMUs 601 to 605 and store similar data segments,respectively, except the absolute location of LMU 703 has changed. X3Dmemory 700 also includes an array of memory units that are eachconfigured sequentially as LMUs 709, 710, 711, 712, 713, 714, 715, 716,706, 707, and 708. LMUs 706 to 716 are similar to LMUs 406 to 416 andstore similar data segments, respectively, except the absolute locationof LMU 708 has changed. As shown in FIG. 7 , row (or section) 750 mayinclude any additional number of empty SMUs, and row 755 may include anyadditional number of empty LMUs.

After the next iteration of wear-leveling is performed on X3D memory 600to result in X3D memory 700, the third memory unit in row 750 is nowconfigured as LMU 708 storing data segment 13 (warm/cold data).Similarly, the third memory unit in row 755 is now configured as SMU 703storing data segment 3 (hot data). In effect, the second iteration ofwear-leveling swaps the locations of SMU 403 and LMU 408 (see FIG. 4 )to result in the post wear-leveling locations of SMU 703 and SMU 708.

FIG. 7B shows a circular representation of the X3D memory 700 after athird iteration of wear-leveling has been performed on X3D memory 400with an arrow 780 illustrating how a fourth iteration of wear-levelingwill be performed on X3D memory 700. The circular representation of X3Dmemory 700 shown in FIG. 7B is structured similar to and stores similardata segments as the circular representation of X3D memory 700 shown inFIG. 7A, except that in X3D memory 700, the memory unit that stores datasegment 3 (e.g., SMU 703) and the memory unit that stores data segment13 (e.g., SMU 708) have switched locations.

As shown in FIG. 7B, SMUs 704-705 remain in their original memory unitlocations and SMUs 701 and 702 remains moved from the beginning of thearray of SMUs to the end of the array of SMUs. However, SMU 703 hasmoved from the beginning of the array of SMUs to the end of the array ofSMUs. The order of the array of memory units configured as SMUs becomesSMU 704, SMU 705, SMU 701, SMU 702, and SMU 703. Similarly, LMUs 709 to716 remain in their original memory unit locations (e.g., the SMUs409-416), and LMUs 706 and 707 remains moved from the beginning of thearray of LMUs to the end of the array of LMUs. However, LMU 708 hasmoved from the beginning of the array of LMUs to the end of the array ofLMUs.

After the third iteration of wear-leveling has been performed to createX3D memory 700, the array of memory units configured as SMUs remaincontiguous to each other in that the SMUs are still adjacent to eachother without any interleaving LMUs. Similarly, the array of memoryunits configured as LMUs also remain contiguous to each other in thatthe LMUs are still adjacent to each other without any interleaving SMUs.The order of the data segments stored in the array of SMUs and LMUs arealso maintained relative to the locations of the other SMUs in acircular fashion.

As indicated by arrow 780, a fourth iteration of wear-leveling comprisesrelocating a first SMU (e.g., SMU 704) to a memory unit after a last SMU(e.g. SMU 703) and relocating a first LMU (e.g., LMU 709) to a memoryunit after the last LMU (e.g., LMU 708). Such an embodiment ofwear-leveling amounts to switching the location of the first SMU 704with the location of the first LMU 709. Arrow 780 points to SMU 704 andLMU 709 in X3D memory 700 that will be relocated during the fourthiteration of wear-leveling. After the fourth iteration of wear-leveling,the locations of SMU 704, storing hot data segment 4, and LMU 709,storing warm/cold data segment 14, will be swapped in X3D memory 700.Therefore, the embodiments of wear-leveling disclosed herein that switchlocations of SMU 704 and LMU 709 facilitate ensuring that the locationsof SMU 704 and LMU 709 are accessed at a similar frequency throughoutthe lifetime of X3D memory 700. In an embodiment, location data (e.g.,location data 174) associated with the SMUs and LMUs may be updated toreflect the fourth iteration of wear-leveling. For example, the newlocations of SMU 704 and/or LMU 709 may be updated after the fourthiteration of wear-leveling is complete.

FIGS. 8A and 8B illustrate representations of an X3D memory 800 after afourth iteration of wear-leveling has been performed on the X3D memory400. FIG. 8A shows a grid representation of the X3D memory 800 afteranother iteration of wear-leveling has been performed on the X3D memory700. The grid representation of X3D memory 800 is similar to the gridrepresentation of X3D memory 700, except that in X3D memory 800, thememory unit that stores data segment 4 (e.g., SMU 804) and the memoryunit that stores data segment 14 (e.g., SMU 809) have switchedlocations.

X3D memory 800 includes an array of memory units that are eachconfigured sequentially as SMUs 805, 801, 802, 803, and 804. SMUs 801 to805 are similar to SMUs 701 to 705 and store similar data segments,respectively, except the absolute location of SMU 804 has changed. X3Dmemory 800 also includes an array of memory units that are eachconfigured sequentially as LMUs 810, 811, 812, 813, 814, 815, 816, 806,807, 808, and 809. LMUs 806 to 816 are similar to LMUs 406 to 416 andstore similar data segments, respectively, except the absolute locationof LMU 809 has changed. As shown in FIG. 8 , row (or section) 850 mayinclude any additional number of empty SMUs, and row 855 may include anyadditional number of empty LMUs.

After the next iteration of wear-leveling is performed on X3D memory 700to result in X3D memory 800, the fourth memory unit in row 850 is nowconfigured as LMU 809 storing data segment 14 (warm/cold data).Similarly, the fourth memory unit in row 855 is now configured as SMU804 storing data segment 4 (hot data). In effect, the second iterationof wear-leveling swaps the locations of SMU 404 and LMU 409 (see FIG. 4) to result in the post wear-leveling locations of SMU 804 and SMU 806.

FIG. 8B shows a circular representation of the X3D memory 800 after afourth iteration of wear-leveling has been performed on X3D memory 400.The grid representation of X3D memory 800 shown in FIG. 8B is structuredsimilar to and stores similar data segments as the circularrepresentation of X3D memory 800 shown in FIG. 8A, except that in X3Dmemory 800, the memory unit that stores data segment 4 (e.g., SMU 804)and the memory unit that stores data segment 14 (e.g., SMU 809) haveswitched locations.

As shown in FIG. 8B, SMU 805 remains in the original memory unitlocations, and SMUs 801 to 803 remain moved from the beginning of thearray of SMUs to the end of the array of SMUs. However, SMU 804 is movedfrom the beginning of the array of SMUs to the end of the array of SMUs.The order of the array of memory units configured as SMUs becomes SMU805, SMU 801, SMU 802, SMU 803, and SMU 804. Similarly, LMUs 810 to 816remain in their original memory unit locations, and LMUs 806 to 808remain moved from the beginning of the array of LMUs to the end of thearray of LMUs. However, SMU 809 is moved from the beginning of the arrayof LMUs to the end of the array of LMUs.

After the fourth iteration of wear-leveling has been performed to createX3D memory 800, the array of memory units configured as SMUs remaincontiguous to each other in that the SMUs are still adjacent to eachother without any interleaving LMUs. Similarly, the array of memoryunits configured as LMUs also remain contiguous to each other in thatthe LMUs are still adjacent to each other without any interleaving SMUs.The order of the data segments stored in the array of SMUs and LMUs arealso maintained relative to the locations of the other SMUs in acircular fashion.

As indicated by arrow 880, a fifth iteration of wear-leveling comprisesrelocating a first SMU (e.g., SMU 805) to a memory unit after a last SMU(e.g. SMU 804) and relocating a first LMU (e.g., LMU 810) to a memoryunit after the last LMU (e.g., LMU 809). Such an embodiment ofwear-leveling amounts to switching the location of the first SMU 805with the location of the first LMU 810. Arrow 880 points to SMU 805 andLMU 810 in X3D memory 800 that will be relocated during the fifthiteration of wear-leveling. After the fifth iteration of wear-leveling,the locations of SMU 805, storing hot data segment 5, and LMU 810,storing warm/cold data segment 15, will be swapped in X3D memory 800.Therefore, the embodiments of wear-leveling disclosed herein that switchlocations of SMU 805 and LMU 810 facilitate ensuring that the locationsof SMU 805 and LMU 810 are accessed at a similar frequency throughoutthe lifetime of X3D memory 800. In an embodiment, location data (e.g.,location data 174) associated with the SMUs and LMUs may be updated toreflect the fifth iteration of wear-leveling. For example, the newlocations of SMU 805 and/or LMU 806 may be updated after the fifthiteration of wear-leveling is complete.

FIGS. 9A and 9B illustrate representations of an X3D memory 900 after afifth iteration of wear-leveling has been performed on the X3D memory400. FIG. 9A shows a grid representation of the X3D memory 900 afteranother iteration of wear-leveling has been performed on the X3D memory800. The grid representation of X3D memory 900 is similar to the gridrepresentation of X3D memory 800, except that in X3D memory 900, thememory unit that stores data segment 5 (e.g., SMU 905) and the memoryunit that stores data segment 15 (e.g., SMU 910) have switchedlocations. As shown, the SMUs 901 to 905 have cycled through onerevolution (five iterations, which is equal to the number of SMUsstoring data segments 1 to 5), and the array of memory units configuredas SMUs is once again 901, 902, 903, 904, and 905. The SMUs 901 to 905are at absolute locations that store data segments in the order of 1, 2,3, 4, and 5.

X3D memory 900 includes an array of memory units that are eachconfigured sequentially as SMUs 901, 902, 903, 904, and 905. SMUs 901 to905 are similar to SMUs 401 to 405 and store similar data segments,respectively, except that the absolute location of SMU 905 has changed.X3D memory 900 also includes an array of memory units that are eachconfigured sequentially as LMUs 911, 912, 913, 914, 915, 916, 906, 907,908, 909, and 910. LMUs 910 to 916 are similar to LMUs 406 to 416 andstore similar data segments, respectively, except the absolute locationof LMU 910 has changed. As shown in FIG. 9 , row (or section) 950 mayinclude any additional number of empty SMUs, and row 955 may include anyadditional number of empty LMUs.

After the next iteration of wear-leveling is performed on X3D memory 800to result in X3D memory 900, the fifth memory unit in row 950 is nowconfigured as LMU 910 storing data segment 15 (warm/cold data).Similarly, the fifth memory unit in row 955 is now configured as SMU 905storing data segment 5 (hot data). In effect, the second iteration ofwear-leveling swaps the locations of SMU 405 and LMU 405 (see FIG. 4 )to result in the post wear-leveling locations of SMU 905 and SMU 910.

FIG. 9B shows a circular representation of the X3D memory 900 after afifth iteration of wear-leveling has been performed on X3D memory 400with an arrow 980 illustrating how a sixth iteration of wear-levelingwill be performed on X3D memory 900. The circular representation of X3Dmemory 900 shown in FIG. 9B is structured similar to and stores similardata segments as the circular representation of X3D memory 900 shown inFIG. 9A, except that in X3D memory 900, the memory unit that stores datasegment 5 (e.g., SMU 905) and the memory unit that stores data segment15 (e.g., SMU 910) have switched locations.

As shown in FIG. 9B, SMUs 901 to 905 have been wear-leveled in onerevolution (five iterations) such that the array of memory unitsconfigured as SMUs 901 to 905 is once again in the order of SMU 901,902, 903, 904, and 905. Since there are a greater number of LMUs thanSMUs, the array of memory units configured as LMUs is not yet in theoriginal order. As shown in FIG. 9 , LMUs 911 to 916 remain in theiroriginal memory unit locations, while LMUs 906 to 909 remain moved fromthe beginning of the array of LMUs to the end of the array of LMUs.However, SMU 910 is moved from the beginning of the array of LMUs to theend of the array of LMUs.

After the fifth iteration of wear-leveling has been performed to createX3D memory 900, the array of memory units configured as SMUs remaincontiguous to each other in that the SMUs are still adjacent to eachother without any interleaving LMUs. Similarly, the array of memoryunits configured as LMUs also remain contiguous to each other in thatthe LMUs are still adjacent to each other without any interleaving SMUs.The order of the data segments stored in the array of SMUs and LMUs arealso maintained relative to the locations of the other SMUs in acircular fashion.

X3D memory 900 may restart the rotation of SMUs 901 to 905 in a sixthiteration of wear-leveling performed on X3D memory 900. As indicated byarrow 980, a sixth iteration of wear-leveling comprises relocating afirst SMU (e.g., SMU 901) to a memory unit after a last SMU (e.g. SMU905) and relocating a first LMU (e.g., LMU 911) to a memory unit afterthe last LMU (e.g., LMU 910). Such an embodiment of wear-levelingamounts to switching the location of the first SMU 901) with thelocation of the first LMU 911. Arrow 980 points to SMU 901 and LMU 911in X3D memory 900 that will be relocated during the sixth iteration ofwear-leveling. After the sixth iteration of wear-leveling, the locationsof SMU 901, storing hot data segment 1, and LMU 911, storing warm/colddata segment 16 will be swapped in X3D memory 900. Therefore, theembodiments of wear-leveling disclosed herein that switch locations ofSMU 901 and LMU 911 facilitate ensuring that the locations of SMU 901and LMU 911 are accessed at a similar frequency throughout the lifetimeof X3D memory 900.

FIGS. 10A and 10B illustrate representations of an initial state of X3Dmemory 1000 with an empty memory unit 1016 before wear-leveling has beenperformed on the X3D memory 1000. FIG. 10A shows a grid representationof an X3D memory 1000. The grid representation of X3D memory 1000 issimilar to the grid representation of X3D memory 400 in FIG. 4A.However, a first memory unit in row (or section) 1050 is an empty memoryunit 1016. The empty memory unit 1016 may not be configured as either anSMU or an LMU. In an embodiment, the empty memory unit 1016 isconfigured as either an SMU or an LMU, but still does not store data.Although only one empty memory unit 1016 is shown in FIGS. 10A-B, theremay be multiple empty memory units 1016 in the X3D memory 1000.

Similar to X3D memory 400, X3D memory 1000 includes an array of memoryunits that are each configured sequentially as SMUs 1001 to 1005. In anembodiment, SMUs 1001 to 1005 are each similar to SMU 210. In row 1050,the second memory unit through the sixth memory unit are each SMUs 1001to 1005, respectively. As shown in FIG. 10A, SMUs 1001 to 1005 eachrespectively stores data segments 1 to 5 of a file, similar to SMUs 401to 405. For example, data segments 1 to 5 represent sequential datasegments of an ordered FTL table (hot data). Row 1050 also includesempty SMUs, such as SMU 1037, that do not store data.

Similar to X3D memory 400, X3D memory 1000 also includes an array ofmemory units that are each configured sequentially as LMUs 1006 to 1015.In an embodiment, LMUs 1006 to 1015 are each similar to LMU 215. In row1055, the first memory unit through the tenth memory unit are each LMUs1006 to 1015, respectively. LMUs 1006 to 1015 each respectively storesdata segments 11 to 20 of a file, similar to LMUs 406 to 415. Forexample, data segments 11-20 represent sequential data segments of amovie file (warm/cold data). Row 1055 also includes empty LMUs, such asLMU 1039, that do not store data. In an embodiment, the wear-levelingperformed on X3D memory 1000 is similar to the wear-leveling performedon X3D memory 400. However, instead of the first SMU (e.g, SMU 1001)being swapped with the first LMU (e.g., LMU 1006), the wear-levelingperformed to result in X3D memory 1100 comprises relocating the firstLMU (e.g., LMU 1006) to the location of the empty memory unit 1016,relocating the first SMU (e.g., SMU 1001) to the memory unit after thelast SMU (e.g., SMU 1037), and erasing the original location of thefirst SMU (e.g., SMU 1001) so that the original location of the firstSMU becomes the empty memory unit 1016.

FIG. 10B shows a circular representation of X3D memory 1000 with arrows1080 and 1090 illustrating how a first iteration of wear-leveling willbe performed on X3D memory 1000. The circular representation of X3Dmemory 1000 shown in FIG. 10B is structured similar to and storessimilar data segments as the grid representation of X3D memory 1000shown in FIG. 10A. As shown in FIG. 10B, X3D memory 1000 comprises anempty memory unit 1016 that is disposed between the end of the array ofmemory units configured as LMUs 1006 to 1015 (e.g., after LMU 1015) andthe beginning of the array of memory units configured as SMUs 1001 to1005 (e.g., before SMU 1005).

In an embodiment, the wear-leveling performed on X3D memory 1000 issimilar to the wear-leveling performed on X3D memory 400. However,instead of the first SMU (e.g, SMU 1001) being swapped with the firstLMU (e.g., LMU 1006), the wear-leveling performed to result in X3Dmemory 1100 comprises relocating the first LMU (e.g., LMU 1006) to thelocation of the empty memory unit 1016, relocating the first SMU (e.g.,SMU 1001) to the memory unit after the last SMU (e.g., SMU 1005), anderasing the original location of the first SMU (e.g., SMU 1001) so thatthe original location of the first SMU becomes the empty memory unit1016. X3D memory 1000 shown in FIG. 10B does not include any empty SMUsor empty LMUs (although X3D memory 1000 shown in FIG. 10A does).However, the last contiguous SMU is considered the last SMU, regardlessof whether the SMU stores data or not. Similarly, the last contiguousLMU is considered the last LMU, regardless of whether the LMU storesdata or not.

For example, relocating the first LMU 1006 to the location of the emptymemory unit 1016 comprises writing data segment 11 to the empty memoryunit. Relocating the first SMU 1001 to the memory unit after the lastSMU comprises writing data segment 1 to LMU 1006. Data segment 1 may beerased from the previous location of the first SMU 1001 so that theprevious location of the first SMU 1001 becomes the empty memory unit1016.

A first iteration of wear-leveling is shown by arrows 1080 and 1090.Arrow 1080 shows LMU 1006, storing data segment 11, being relocated tothe empty memory unit 1016 in the first iteration of wear-leveling.Arrow 1090 shows the SMU 1001, storing data segment 1, being relocatedto the memory unit after the last SMU (e.g., SMU 1005), where LMU 1006is currently located. This wear-leveling process has the same effect ofswitching locations of hot data and cold data as the wear-levelingprocess disclosed in FIGS. 4-9 , but additionally switches locations ofthe empty memory unit 1016. The empty memory unit 1016 is involved inthe wear-leveling process as data is written to and from the emptymemory unit 1016 to the location of another SMU or LMU during eachiteration of wear-leveling. This helps ensure that the locations of theempty memory unit 1016, SMU 1001, and LMU 1006 are accessed at asubstantially equal frequency throughout the lifetime of X3D memory1000. In an embodiment, location data (e.g., location data 174)associated with the SMUs and LMUs may be updated to reflect the firstiteration of wear-leveling.

FIGS. 11A and 11B illustrate representations of an X3D memory 1100 aftera first iteration of wear-leveling has been performed on the X3D memory1000. FIG. 11A shows a grid representation of the X3D memory 1100. Thegrid representation of X3D memory 1100 is similar to the gridrepresentation of X3D memory 1000, except that the first LMU (e.g., LMU1106) is relocated to the memory unit after the last LMU (e.g., LMU1115). The memory unit after LMU 1115 is the empty memory unit (e.g.,empty memory unit 1116). The first SMU (e.g., SMU 1101) is relocated tothe memory unit after the last SMU (e.g., SMU 1105), which is theoriginal location of LMU 1116. The empty memory unit 1116 has beenrelocated to the original location of the first SMU.

X3D memory 1100 includes an array of memory units that each configuredsequentially as SMUs 1102, 1103, 1104, 1105, and 1101. SMUs 1101 to 1105are similar to SMUs 1000 to 1005 and store similar data segments,respectively, except that the absolute location of SMU 1101 has changed.X3D memory 1100 also includes an array of memory units that are eachconfigured sequentially as LMUs 1107, 1108, 1109, 1110, 1111, 1112,1113, 1114, 1115, and 1106. LMUs 1106 to 1115 are similar to LMUs 1000to 1015 and store similar data segments, respectively, except that theabsolute location of LMU 1106 has changed.

After the first iteration of wear-leveling, as shown in FIG. 11A, thefirst memory unit in row (or section) 1150 is LMU 1106 storing datasegment 11 (warm/cold data), and the first memory unit in row 1155 isSMU 1001 storing data segment 1 (hot data). The empty memory unit 1116is then relocated to the original location of the first SMU.

FIG. 11B shows a circular representation of X3D memory 1100 with arrows1180 and 1190 illustrating how a second iteration of wear-leveling willbe performed on X3D memory 1100. The circular representation of X3Dmemory 1100 shown in FIG. 11B is structured similar to and storessimilar data segments as the grid representation of X3D memory 1100shown in FIG. 11A. As shown in FIG. 11B, X3D memory 1100 comprises anempty memory unit 1116 that is disposed between the end of the array ofmemory units configured as LMUs 1106 to 1115 (e.g., after LMU 1106) andthe beginning of the array of memory units configured as SMUs 1101 to1105 (e.g., before SMU 1102).

A second iteration of wear-leveling is shown by arrows 1180 and 1190. Inan embodiment, the second iteration wear-leveling performed on X3Dmemory 1100 is similar to the first iteration of wear-leveling performedon X3D memory 1000. Arrow 1180 shows LMU 1107, storing data segment 12,being relocated to the empty memory unit 1116. Arrow 1190 shows the SMU1102, storing data segment 2, being relocated to the memory unit afterthe last SMU (e.g., SMU 1101). The memory unit after the last SMU iswhere LMU 1107 is currently located. In an embodiment, location data(e.g., location data 174) associated with the SMUs and LMUs may beupdated to reflect the second iteration of wear-leveling.

FIGS. 12A and 12B illustrate representations of an X3D memory 1200 aftera second iteration of wear-leveling has been performed on the X3D memory1000. FIG. 12A shows a grid representation of the X3D memory 1200. Thegrid representation of X3D memory 1200 is similar to the gridrepresentation of X3D memory 1100, except that the first LMU (e.g., LMU1207) is relocated to the memory unit after the last LMU (e.g., LMU1206). The memory unit after the last LMU is the empty memory unit(e.g., empty memory unit 1216). The first SMU (e.g., SMU 1202) isrelocated to the memory unit after the last SMU (e.g., SMU 1201), whichis the original location of LMU 1116. The empty memory unit 1216 is thenrelocated to the original location of the first SMU.

X3D memory 1200 includes an array of memory units that each configuredsequentially as SMUs 1203, 1204, 1205, 1201, and 1202. SMUs 1201 to 1205are similar to SMUs 1000 to 1005 and store similar data segments,respectively, except that the absolute location of SMU 1202 has changed.X3D memory 1200 also includes an array of memory units that are eachconfigured sequentially as LMUs 1208, 1209, 1210, 1211, 1212, 1213,1214, 1215, 1206, and 1207. LMUs 1206 to 1215 are similar to LMUs 1000to 1015 and store similar data segments, except that the absolutelocation of LMU 1207 has changed.

After the second iteration of wear-leveling, as shown in FIG. 12A, thesecond memory unit in row (or section) 1250 is LMU 1207 storing datasegment 12 (warm/cold data), and the second memory unit in row 1255 isSMU 1202 storing data segment 2 (hot data). The empty memory unit 1216is then relocated to the original location of the first SMU.

FIG. 12B shows a circular representation of X3D memory 1200 with arrows1280 and 1290 illustrating how a third iteration of wear-leveling willbe performed on X3D memory 1200. The circular representation of X3Dmemory 1200 shown in FIG. 12B is structured similar to and storessimilar data segments as the grid representation of X3D memory 1200shown in FIG. 12A, except that the X3D memory 1200 is shown in acircular fashion. As shown in FIG. 12B, X3D memory 1200 comprises anempty memory unit 1216 that is disposed between the end of the array ofmemory units configured as LMUs 1206 to 1215 (e.g., after LMU 1207) andthe beginning of the array of memory units configured as SMUs 1201 to1205 (e.g., before SMU 1203).

A third iteration of wear-leveling is shown by arrows 1280 and 1290. Inan embodiment, the wear-leveling performed on X3D memory 1200 is similarto the wear-leveling performed on X3D memory 1100. Arrow 1280 shows LMU1208, storing data segment 13, being relocated to the empty memory unit1216 in the second iteration of wear-leveling. Arrow 1290 shows the SMU1203, storing data segment 3, being relocated to the memory unit afterthe last SMU (e.g., SMU 1202), where LMU 1208 is currently located. Inan embodiment, location data (e.g., location data 174) associated withthe SMUs and LMUs may be updated to reflect the third iteration ofwear-leveling.

Although only three iterations of wear-leveling have been shown in FIGS.10-12 , it should be appreciated that any number of iterations ofwear-leveling can be performed on X3D memory 1000. The data segmentsstored at the SMUs and LMUs of X3D memory 1000 may continue to be cycledthrough and swapped with data stored at other the SMUs and LMUs so longas the SMUs and LMUs maintain their contiguous nature throughout theiterations of wear-leveling.

The X3D memories shown in FIGS. 4-12 only comprise SMUs, LMUs, and emptymemory units. However, an X3D memory may also comprise a MMU configuredto store warm data, and any other type of memory unit configured tostore any other type of data. In an embodiment, an X3D memory maycomprise a plurality of sections (or zones) of different types of memoryunits. Each section may be configured to store a certain temperature ofdata. For example, a first section comprises SMUs configured to storehot data, a second section comprises MMUs configured to store warm data,a third section comprises LMUs configured to store cold data, and/or afourth section comprises empty memory units that are not specificallyconfigured to store any type of data. The memory units in each of thesections are contiguous with each other. In an embodiment, multiplesections may be configured to store the same type of data.

FIGS. 13A and 13B illustrate representations of X3D memory 1300 havemultiple sections for storing various types of data. FIG. 13A shows agrid representation of X3D memory 1300. X3D memory 1300 includes row (orsection) 1350, row 1352, and row 1355. Row 1350 includes an array ofmemory units that are each configured sequentially as SMUs 1301 to 1305,which respectively stores data segments 1 to 5. Row 1352 includes anempty memory unit 1306, and any array of memory units that are eachconfigured sequentially as MMUs 1307 to 1309, which respectively storesdata segments 7 to 9. Row 1355 includes an array of empty memory units1310 to 1312, and an array of memory units that are each configuredsequentially as LMUs 1313 to 1316, which respectively stores datasegments 13 to 16. Empty memory units 1306 and 1310 to 1312 are notconfigured as either SMUs, MMUs, or LMUs, and do not store any data. Asshown in FIG. 13 , the SMUs are contiguous with each other, the MMUs arecontiguous with each other, and the LMUs are contiguous with each other.

FIG. 13B shows a circular representation of X3D memory 1300 with arrows1380, 1385, and 1390 illustrating how an iteration of wear-leveling willbe performed on X3D memory 1300. The circular representation of X3Dmemory 1300 illustrates how the data structures stored in X3D memory1300 are logically organized by the section (or row) and into a circlesuch that wear-leveling may be performed within each section and betweeneach section. In an embodiment, the wear-leveling performed on X3Dmemory 1300 is similar to the wear-leveling performed on X3D memory 400and 1000.

Arrow 1380 shows SMU 1301, storing data segment 1, being relocated tothe empty memory unit 1306 during an iteration of wear-leveling. Arrow1385 shows MMU 1307, storing data segment 7, being relocated to theempty memory unit 1310 during an iteration of wear-leveling. Arrow 1390shows LMU 1313, storing data segment 13, being relocated to the positionwhere SMU 1301 used to be located prior to relocating to the emptymemory unit 1306. In an embodiment, SMU 1301 is relocated first, MMU1307 is relocated second, and LMU 1313 is relocated third, to makeefficient use of the empty memory units available without having to usea buffer to temporarily store the data. Therefore, the circularrepresentation of X3D memory 1300 shows the embodiments of wear-levelingdisclosed herein help maintain the data structure for the data stored ineach of the sections and maintain the relative order of the data in eachof the sections.

In an embodiment, when a user of an HMD (e.g., HMD 100) searches fordata to perform a read and/or write request on the data, a processor(e.g., processor 130) determines whether the data is stored on the X3Dmemory (e.g., X3D memory 133) or the secondary memory (e.g., secondarymemory 140). In an embodiment, the X3D memory stores hotter data thanthe secondary memory. For example, the processor searches the locationdata (e.g., location data 174) to determine whether the data is storedin the X3D memory. The processor may then identify the location of thedata in the SMUs or the LMUs if the processor determines that the datais stored in the X3D memory. Otherwise, the processor searches thesecondary memory for the requested data. When the data that is searchedfor is stored in the X3D memory, the data can be written directly to thelocation of the data as X3D memory supports the in-place updating ofdata. The embodiments of wear-leveling disclosed herein help lengthenthe lifespan of an X3D memory by ensuring that all of the memory cellsof the X3D memory are read, written to, written from, and programmed atapproximately the same rate. This way, all of the memory cells of theX3D memory will wear out at the same rate, instead of the memory cellsstoring hot data wearing out much faster than the memory cells storingcold data. When all of the memory cells of the X3D memory wear out atthe same rate, the lifespan of the X3D memory is significantlyincreased.

Embodiments of the present disclosure also ensure that the order of thedata structures stored at the X3D memory are maintained relative to eachother after each iteration of wear-leveling. Because the X3D memory isnon-volatile, the hot data stored at SMUs will be stored as long asneeded and is not dependent on the SMUs being powered.

In an embodiment, the disclosure includes a method for wear-leveling inan X3D memory, comprising a means for detecting a trigger event, whereinthe X3D memory comprises a first section of memory units and a secondsection of memory units, the first section of memory units comprises aplurality of contiguous memory units configured to store data of a firsttype, and the second section of memory units comprises a plurality ofmemory units configured store data of a second type, and in response todetecting the trigger event, a means for relocating data stored in afirst memory unit of the first section of memory units to a memory unitadjacent to a last memory unit of the first section of memory units, anda means for relocating data stored in a first memory unit of the secondsection of memory units to a memory unit adjacent to a last memory unitof the second section of memory units.

In an embodiment, the disclosure includes an X3D memory, comprising aplurality of SMUs stored in contiguous locations in the X3D memory andconfigured to store data of a first type, and a plurality of LMUs storedin contiguous locations in the X3D memory and configured to store dataof a second type, wherein wear-leveling of the X3D memory comprises ameans for detecting a trigger event, in response to the trigger event, ameans for relocating data stored in a first SMU of the plurality of SMUsto a memory unit adjacent to a last SMU of the plurality of SMUs,wherein the plurality of SMUs are stored in contiguous locations in theX3D memory, and a means for relocating data stored in a first LMU of theplurality of LMUs to a memory unit adjacent to a last LMU of theplurality of LMUs, wherein the plurality of LMUs are stored incontiguous locations in the X3D memory.

In an embodiment, the disclosure includes an HMD, comprising an X3Dmemory comprising a first plurality of MUs and a second plurality ofMUs, a means for detecting a trigger event that triggers an iteration ofwear-leveling to be performed on the X3D memory, wherein data stored ina first MU of the first plurality of MUs is relocated to a MU adjacentto a last MU of the first plurality of MUs, wherein the first pluralityof MUs are stored in contiguous locations in the X3D memory, whereindata stored in a first MU of the second plurality of MUs is relocated toa MU adjacent to a last MU of the second plurality of MUs, and whereinthe second plurality of MUs are stored in contiguous locations in theX3D memory.

While several embodiments have been provided in the present disclosure,it should be understood that the disclosed systems and methods might beembodied in many other specific forms without departing from the spiritor scope of the present disclosure. The present examples are to beconsidered as illustrative and not restrictive, and the intention is notto be limited to the details given herein. For example, the variouselements or components may be combined or integrated in another systemor certain features may be omitted, or not implemented.

In addition, techniques, systems, subsystems, and methods described andillustrated in the various embodiments as discrete or separate may becombined or integrated with other systems, modules, techniques, ormethods without departing from the scope of the present disclosure.Other items shown or discussed as coupled or directly coupled orcommunicating with each other may be indirectly coupled or communicatingthrough some interface, device, or intermediate component whetherelectrically, mechanically, or otherwise. Other examples of changes,substitutions, and alterations are ascertainable by one skilled in theart and could be made without departing from the spirit and scopedisclosed herein.

What is claimed is:
 1. A method performed by a processor to improvewear-leveling in a cross-point memory, comprising: detecting, by aprocessor coupled to the cross-point memory, a first trigger event, thecross-point memory comprising a first section of memory units, a secondsection of memory units, and an empty memory unit positioned between thefirst section of memory units and the second section of memory units tocreate logical contiguity of data stored in the first section of memoryunits, the second section of memory units, and the empty memory unit,the first section of memory units comprising a plurality of logicallycontiguous memory units configured to store data of a first type, thedata of the first type being hot data that is frequently accessed, thehot data stored at each memory unit of the first section of memory unitscomprising a portion of a flash translation layer (FTL) table; and thesecond section of memory units comprising a plurality of logicallycontiguous memory units configured to store data of a second type, thedata of the second type being warm data or cold data, the warm data orthe cold data comprising data that is less frequently accessed than theportion of the FTL that is the hot data; and in response to detectingthe first trigger event: relocating, by the processor, data of thesecond type stored in a first memory unit of the second section ofmemory units to the empty memory unit; relocating, by the processor,data of the first type stored in a first memory unit of the firstsection of memory units to the first memory unit of the second sectionof memory units; and erasing, by the processor, the data of the firsttype stored in the first memory unit of the first section of memoryunits, the first memory unit of the first section of memory unitsbecoming the empty memory unit after the first trigger event, the emptymemory unit remaining positioned between the first section of memoryunits and the second section of memory units after the first triggerevent, the memory units in the first section of memory units remaininglogically contiguous after the first trigger event, and the memory unitsin the second section of memory units remaining logically contiguousafter the first trigger event; and in response to detecting a secondtrigger event after the first trigger event; relocating, by theprocessor, data of the second type stored in a second memory unit of thesecond section of memory units to the empty memory unit; relocating, bythe processor, data of the first type stored in a second memory unit ofthe first section of memory units to the second memory unit of thesecond section of memory units; and erasing, by the processor, the dataof the first type stored in the second memory unit of the first sectionof memory units, the second memory unit of the first section of memoryunits becoming the empty memory unit after the second trigger event, theempty memory unit remaining positioned between the first section ofmemory units and the second section of memory units after the secondtrigger event, the memory units in the first section of memory unitsremaining logically contiguous after the second trigger event, and thememory units in the second section of memory units remaining logicallycontiguous after the second trigger event.
 2. The method of claim 1,wherein the first trigger event and the second trigger event occur whenat least one of a frequency of accesses to one or more of the memoryunits in the first section of memory units reaches a pre-determinedthreshold.
 3. The method of claim 1, wherein the first trigger event andthe second trigger event occur according to a pre-determined scheduleindicating when a next iteration of wear- leveling needs to be performedon the cross-point memory.
 4. The method of claim 3, further comprisingrelocating the data stored in the first memory unit of the first sectionof memory units to a location of the first memory unit of the secondsection of memory units.
 5. The method of claim 1, further comprisingrelocating the data stored in the first memory unit of the secondsection of memory units to a location of the first memory unit of thefirst section of memory units.
 6. The method of claim 5, wherein thefirst section of memory units comprises a plurality of small memoryunits (SMUs) configured to store the data of the first type, wherein thesecond section of memory units comprises a plurality of large memoryunits (LMUs) configured to store the data of the second type, whereinthe cross-point memory further comprises a third section of memoryunits, and wherein the third section of memory units comprises aplurality of medium memory units (MMUs) configured to store data of athird type.
 7. The method of claim 1, wherein a first access frequencyis a first range of access frequencies, and wherein a second accessfrequency is a second range of access frequencies.
 8. A cross-pointmemory system, comprising: a plurality of small memory units (SMUs)stored in logically contiguous locations in the cross-point memorysystem and configured to store data of a first type, the data of thefirst type being hot data that is frequently accessed, the hot datastored at each of the SMUs comprising a portion of a flash translationlayer (FTL) table; a plurality of large memory units (LMUs) stored inlogically contiguous locations in the cross-point memory system andconfigured to store data of a second type, the data of the second typebeing warm data or cold data, the warm data or the cold data comprisingdata that is less frequently accessed than the portion of the FTL thatis the hot data; an empty memory unit positioned between the pluralityof SMUs and the plurality of LMUs to create a logical contiguity of datastored in the plurality of SMUs, the plurality of LMUs, and the emptymemory unit; and at least one processor configured to: detect a firsttrigger event; in response to the first trigger event: relocate data ofthe second type stored in a first LMU of the plurality of LMUs to theempty memory unit; relocate data of the first type stored in a first SMUof the plurality of SMUs to the first LMU of the plurality of LMUs; anderase the data of the first type stored in the first SMU of theplurality of SMUs, the first SMU of the plurality of SMUs becoming theempty memory unit after the First trigger event, the empty memory unitremaining positioned between the plurality of SMUs and the plurality ofLMUs after the first trigger event, the memory units in the plurality ofSMUs remaining logically contiguous after the first trigger event, andthe memory units in the plurality of LMUs remaining logically contiguousafter the first trigger event; detect a second trigger event after thefirst trigger event; and in response to the second trigger event:relocate data of the second type stored in a second LMU of the pluralityof LMUs to the empty memory unit; relocate data of the first type storedin a second SMU of the plurality of SMUs to a location of the secondLMU; and erase the data of the first type stored in the second SMU, thesecond SMU becoming the empty memory unit after the second triggerevent, the empty memory unit remaining positioned between the pluralityof SMUs and the plurality of LMUs after the second trigger event, thememory units in the plurality of SMUs remaining logically contiguousafter the second trigger event, and the memory units in the plurality ofLMUs remaining logically contiguous after the second trigger event. 9.The cross-point memory system of claim 8, wherein the empty memory unitcomprises one or more empty memory units that are contiguously disposedin between the plurality of LMUs and the plurality of SMUs.
 10. Thecross-point memory system of claim 8, wherein the at least one processoris further configured to: update location data of the cross-point memorysystem to indicate that the data stored in the first SMU has beenrelocated to a location of the memory unit adjacent to the last SMU; andupdate the location data of the cross-point memory system to indicatethat the data stored in the first LMU has been relocated to a locationof the memory unit adjacent to the last LMU.
 11. The cross-point memorysystem of claim 8, wherein the data of the first type is data that hasbeen accessed within a predetermined time period.
 12. The cross-pointmemory system of claim 8, further comprising at least one empty buffermemory unit configured to temporarily store the data stored in the firstLMU while the data in the first SMU is relocated to the memory unitadjacent to the last LMU.
 13. The cross-point memory system of claim 8,further comprising at least one empty buffer memory unit configured totemporarily store the data stored in the first SMU while the data in thefirst LMU is relocated to the memory unit adjacent to the last SMU. 14.The cross-point memory system of claim 8, wherein a first accessfrequency is a first range of access frequencies, and wherein a secondaccess frequency is a second range of access frequencies.
 15. A hybridmemory device (HMD), comprising: a cross-point memory comprising a firstplurality of memory units (MUs) stored in logically contiguous locationsin the cross-point memory, a second plurality of MUs stored in logicallycontiguous locations in the cross-point memory, and an empty memory unitpositioned between the first plurality of MUs and the second pluralityof MUs to create logical contiguity of data stored in the firstplurality of MUs, the second plurality of MUs, and the empty memoryunit, the first plurality of MUs being configured to store data of afirst type, the data of the first type being hot data that is frequentlyaccessed, the hot data stored at each of the first plurality of MUscomprising a portion of a flash translation layer (FTL) table, thesecond plurality of MUs being configured to store data of a second type,the data of the second type being warm data or cold data, the warm dataor the cold data comprising data that is less frequently accessed thanthe portion of the FTL that is the hot data; and a processor coupled tothe cross-point memory and configured to: detect a first trigger eventthat triggers an iteration of wear-leveling to be performed on thecross-point memory; in response to the first trigger event: relocatedata of the second type stored in a first MU of the second plurality ofMUs to a MU adjacent to the empty memory unit; relocate data of thefirst type stored in a first MU of the first plurality of MUs to thefirst MU of the second plurality of MUs; and erase the data of the firsttype stored in the first MU of the first plurality of MUs, the first MUof the first plurality of MUs becoming the empty memory unit after thefirst trigger event, the empty memory unit remaining positioned betweenthe first plurality of MUs and the second plurality of MUs after thefirst trigger event, the first plurality of MUs remaining logicallycontiguous after the first trigger event, and the second plurality ofMUs remaining logically contiguous after the first trigger event; detecta second trigger event; and in response to the second trigger event:relocate data of the second type stored in a second MU of the secondplurality of MUs to the empty memory unit; relocate data of the firsttype stored in a second MU of the first plurality of Ws to a location ofthe second MU of the second plurality of MUs; and erase the data of thefirst type stored in the second MU of the first plurality of Ws, thesecond MU of the first plurality of Ws becoming the empty memory unitafter the second trigger event, the empty memory unit remainingpositioned between the first plurality of MUs and the second pluralityof MUs after the second trigger event, the first plurality of MUsremaining logically contiguous after the second trigger event, and thesecond plurality of Ws remaining logically contiguous after the secondtrigger event.
 16. The HMD of claim 15, further comprising a secondarymemory coupled to the processor and the cross-point memory.
 17. The HMDof claim 15, further comprising a temporary memory coupled to theprocessor and the cross-point memory, wherein the temporary memorycomprises at least one of a location of the first MU of the firstplurality of MUs, a location of the last MU of the first plurality ofMUs, a location of the first MU of the second plurality of MUs, and alocation of the last MU of the second plurality of MUs.
 18. The HMD ofclaim 17, wherein the location of the first MU of the first plurality ofMUs is updated after the data stored in the first MU of the firstplurality of MUs is relocated to a memory unit adjacent to the last MUof the first plurality of MUs, and wherein the location of the first MUof the second plurality of MUs is updated after the data stored in thefirst MU of the second plurality of MUs is relocated to a memory unitadjacent to the last MU of the second plurality of MUs.
 19. The HMD ofclaim 15, wherein the cross-point memory comprises at least one emptybuffer memory unit.
 20. The HMD of claim 15, wherein a first accessfrequency is a first range of access frequencies, and wherein a secondaccess frequency is a second range of access frequencies.